The reduction of semiconductor device geometries necessary for the realisation of very large scale integration (VLSI) circuits requires a reduction in the resistivity of the high-temperature-compatible interconnect materials employed, and to this end metallic silicides, such as titanium, tantalum, tungsten or molybdenum silicide, are increasingly being adopted as an alternative to polysilicon.
A general reduction of process temperatures or times is also desirable to minimise redistribution of dopants and interdiffusion of adjacent layers. Presently, for example, titanium and silicon layers are annealed for some 30 to 40 minutes in order to form titanium disilicide, and the length of such anneal times is disadvantageous. Whilst it has been shown that such anneal times can be reduced, this necessitates the acceptance of a reduction in the conductivity of the titanium disilicide films produced.